How to use EDMA to undertake digital video signal transmit

When the half of buffer of video signal cram, give DSP by FPGA exterior interrupt, can be the random in INT4 ～ INT7, 4 of the corresponding EDMA that start transmission passageways transmit one of passageways to 7. Spark when signal comes, EDMA takes away whole data (FS ＝ 1) , in the meantime, video signal is written to the other in part of buffer ceaselessly. Distinguish amortize into two half, reading is occupied and write data to be absent same a half area, assured the integrality of data.

After transmitting an end, address of the source in transmission parameter group and target address need to produce a change, in this system, source address and target address have a lot of kinds of different cases, cannot change transmission parameter form with link means (LINK ＝ 0b) , and convert discontinuous pattern, interrupt transmission end a TCINT to install for 1, what we use in the system is INT7 incident serve as EDMA spark incident, corresponding ground transmits end code TCC is set for 0111b. Such, after the transmission of 7 ends the passageway when correspondence, EDMA controller will give out to CPU the name is EDMAINT interrupt signal.

How to use EDMA to transmit digital video signal

3, interrupt service program ISR (InterruptServiceRoutines)

3. The 1 function that suspends a program

If CPU is answered,interrupt (default is CPUINT8) , suspend service program with respect to what turn to executive correspondence. EDMA can be changed to transmit parameter group in ISR, for next time transmit prepare. Buffer cent plays two parts to go up, this shows the address of data source has two kinds, and after transmitting an end every time, source address must change the address of another half area, this is typical ping-pong algorithm. Same, the switch to odd field and even field also can use ping-pong algorithm to finish, they decided the alternative of target address.

3. 2 use DSP ／ BIOS to configure tool configuration to interrupt function

Generate BIOS of ／ of a DSP to configure a file, in joining it the project, open configuration file, the HWI that cultivates in Scheduling child in the tree, for HWIINT8 Jiashangzhong breaks function. Those who need an attention is, if configure a file to save the catalog that is in in the project no longer, the Jiashang in must compiling option I option, demonstrate configures the position of the file, otherwise, compiler cannot find the definition that interrupts function.

3. 3 algorithm come true

What the TV signal of our country uses is PAL is made, every are 64 μ S all right, among them, picture signal occupies 52 μ S, if use 12. 288MHz sampling, every get 640 picture signal all right, namely 160 data are unit, in all the data of 640 × 8bit, if use RAM of two IDT7025 double mouth to form buffer of 8Kbyte × 32bit, criterion half area can store 25 digital video signal. Namely, write when buffer full 25 travel hind, FPGA gives DSP signal of tall n of the exterior INT7 that cite a base, spark EDMA begins to transmit data. For transmission convenience, before using FPGA to come in even field signal, write hemistich black n to buffer first, such, the linage of an image is 288, deferent a need is transmitted 12 times, so, when transmitting arrival the 13rd times, must undertake the switch of odd field and even field, in order to change the initiative address of target memory.
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